Process gradients are systematic variations of a parameter over the wafer or die. Most process parameters are effected by process gradients. For example, the oxide thickness may vary systematically from one side of the die to the other. Similarly, for a transistor the threshold voltage may have a systematic variation.
Figure 2.5: Capacitor structure with process gradient.
In Figure 2.5, the previously discussed unit capacitor structure is shown. In the Figure, an oxide thickness gradient is indicated. Due to the process gradient, the average oxide thickness for the four capacitors on the right is different from that of the single capacitor on the left. As a result, a capacitor ratio error will occur. A solution to the problem of process gradients can be achieved with the use of common centroid layout techniques.
Figure 2.6: Common centroid layout using unit capacitors.
For capacitors, a relatively simple solution is offered by the use of
common centroid layout
, especially if the process
gradient is approximately linear.
The layout is illustrated in Figure 2.6.
The capacitors are laid out, so that they have the same centroid. As a
result of the common centroid layout, the capacitors have the same average
or effective gate thickness. To ensure that process gradients can be
approximated linearly, the matched elements should be placed as close
to one another as possible.
If the input offset voltage of an operational amplifier is to be
minimised, a common centroid layout of the input differential
transistors is essential. With optimum layout and design structures,
operational amplifiers with a maximum input offset voltage of 3-4mV
(
) have been demonstrated[Mon86].
One possible common centroid layout solution for an input differential
pair is shown in Figure 2.7[Mal94].
The input transistors have been split into four equal parts, which
are connected in parallel in a suitable manner. This structure has
the advantage over other solutions, that through the interleaved
layout of the transistors, the common source and both drains can
be connected in metal and require no crossovers. This structure
is particularly well suited for input stages with wide input transistors.
Figure 2.7: Interleaved layout of differential pair.
The transistor layout in Figure 2.7 leads to a very compact layout with a common centroid for the two input transistors. A good rule to keep in mind when dimensioning input transistors is, that the transistor matching is proportional to the square root of the gate area[Shy84]. The equivalent input noise of the transistor is inversely proportional to the gate area.
Figure 2.8: Current switching DAC structure.
In the case, where more than two elements have to be matched, a common centroid layout can become cumbersome and impractical. In Figure 2.8, a current switching DAC is illustrated using thermometer decoding[O'L91]. The transistors M1-M4 are the unit current sources of a current switching DAC. To ensure both good differential and integral nonlinearity, an optimum matching is required between the transistors.
A common centroid layout is not possible for the transistors M1-M4 without extreme penalties in area. However, the undesirable gradient effects can yet be minimised by design. In the case of a DAC, knowing which parameter is the most important, differential or integral nonlinearity, it is possible to optimise the decoding.
Figure 2.9: Precision resistor structure.
The use of common centroid layout of resistors is a debatable subject.
In general, resistor structures require more contacts when laid-out as
common centroid layouts. These contacts must also carry current and as
a result, the contact resistance (which is not negligible) effects the
resistor matching. Figure 2.9 shows a precision resistor
structure used in an ADC.
Most analysis and proposed solutions assume that the process gradient is linear. Practical experience indicates that this assumption is sufficient.