Global process variations typically result from errors during the photolithographic processing and etching of the wafers. Similar to all photographic processes, the photo-lithographic processing of silicon is prone to over or under exposure, over or under development etc. Similarly, the etching steps, which follow the photolithographic process, are prone to over or under etching. Characteristics of global process variations are, that they are constant over the entire wafer, i.e. common to all components on the wafer. Typically, global process variations cause degradation of the circuit element matching.
Figure 2.2: Capacitor ratio example.
To examine the consequences of such processing errors and to see, how the
resulting mismatch may be minimised, a pair of matched capacitors with the
desired capacitor ratio 
is examined
(see Figure 2.2).
The area ratio for the capacitors drawn during layout is:
If the poly-silicon is over-etched by 
(such errors may occur
due to variations in the etching time or from changing saturation of the
etching fluid from one wafer batch to the next) then the realised capacitor
ratio, 
, is given by:
Combining Equations 2.6 and 2.7, the relative
error, 
, can be calculated to estimate the achievable matching:
The consequences of such errors can be illustrated by a typical example.
Assume that a capacitor with dimension 
is used,
and that typical etching variations 
must be
accepted. The wavelength of blue light is approximately 460nm, thus an
error of 100nm is less than one quarter of the wavelength. Despite the
small magnitude of this error, it can result in serious problems in high
precision circuits. For a capacitor ratio of 4:1, Equation 2.9
gives the following error:
If the two capacitors were to be used in a data converter, then this
error would correspond to 6.2bits
0.5bit of linearity. Evidently,
the use of such simple structures is not appropriate for the design
of precision circuits.
Figure 2.3: Using unit capacitors.
The error can be eliminated or at least dramatically reduced by the use of unit capacitors (see Figure 2.3). Using unit capacitors, the area of each capacitor is reduced by the same factor. Therefore, the ratio remains unchanged. The use of unit elements requires that the lowest common denominator of the desired ratio is feasible to implement.
Figure 2.4: Non-unit capacitor structure.
If the required ratio can not be achieved with a reasonable number of
unit elements, then a non unit capacitor (or element) must be used. For
example, a ratio of 11:13.3 requires 243 unit capacitors, which is not
realistic. If non-unit capacitors are used, the matching is sensitive to
global lithographic variations. Consequently, the capacitor ratio depends
on such factors as over or under etching. The magnitude of these errors
can be minimised with the use of optimum dimensioning
(see Figure 2.4). A global etching error in this
structure introduces the relative error, :
Equation 2.13 gives a good approximation for the mismatch
due to etching errors. Now, this equation is used to find the dimensions
for X2 and X3, which give the minimum sensitivity of to
. The optimum is found by taking the first derivative of
with respect to and setting the equation equal to zero:
The first term of Equation 2.14 is the ratio of
the perimeters, and the second term is the ratio of the areas.
If Equation 2.14 equals zero, then the ratio of
the perimeters must equal the ratio of the areas. Solving this
equation to find the optimum dimensioning for the capacitors gives:
Finally, solving the quadratic equation gives:
One restriction on the choice of non-unit capacitors can readily be
seen from Equation 2.16. If the solutions to the quadratic
equation are to be real, then the capacitor ratio must be
greater than 1. This means that the smaller capacitor should correspond
to the unit capacitor, and the larger capacitor should be the non-unit
element. If Equation 2.16 is used to dimension the non-unit
capacitors, then a layout is achieved, which has minimum sensitivity to
photolithographic errors and etching variations.
The previously discussed example of a capacitor ratio 11:13.3 would be implemented using 11 unit capacitors for one capacitor and 12 units plus one non-unit for the second capacitor.
Unfortunately, this solution assumes isotropic etching.
From Equation 2.16, long and narrow capacitors result
for ratios 
and 
,
when 
is small. Unfortunately, such capacitors are very
sensitive to anisotropic etching and photolithographic
processing
.
Capacitors of value should be realised using a
square capacitor. Similarly, capacitors in the range should be implemented as one unit capacitor and one capacitor of value
. The increased sensitivity of these structures to isotropic
errors is more than compensated by the improved performance with respect
to anisotropic processing[O'L91].