The MOS fabrication process is a long sequence of chemical processing
steps, which results in device characteristics following a Gaussian
(normal) distribution. The sources of these variations are many;
variations in doping densities, processing temperatures, etc. The device
parameters of any MOS process will only be guaranteed within a 
limit of the process target parameters.
In this chapter, we discuss the effects of random process variations on precision layout and characterise common properties of such parameter variations. The effects may be minimised by a) better processing resulting in lower standard deviations or b) layout structures less sensitive to a specific variation. Naturally, the discussion is focussed on analog rather than digital devices. A good analog process may be the choice for a specific analog design problem. However, for high performance mixed analog and digital circuits, this may not be a viable solution. Therefore, this chapter focuses on less sensitive layout structures. The aim of the discussion is to find optimal layout methods for reducing the influence of process tolerances on precision components.
In this chapter, we categorise process variations as
.