Element matching is important in almost all analog circuits. In this Section, we discuss the basic principles of element matching and useful structures for matching. To illustrate element matching, the basic amplifier circuit in Figure 2.1 is analysed.
Figure 2.1: Basic amplifier circuit.
The gain of this circuit, 
, is given by:
If we use m unit resistors
to realise R1 and n to realise R2, then the gain
is given by:
The actual value of the unit resistor does not occur in the expression.
However, the value of each resistor displays some statistical variation.
Assuming a Gaussian distribution of the variation, we can calculate the
acceptable standard deviation of the resistor value using the following
approximation:
The approximation only holds for small values of 
.
The gain of the amplifier should remain within the required specification
for a 
variation of the resistances in order to guarantee good
yield. A boundary by a Gaussian distribution corresponds to a
yield loss of 0.13% for this resistor alone. If the circuit consists of
many other elements, the yield losses combine. As a result, an extremely
high yield must be required for each individual circuit element. This is
illustrated, when using the boundary condition in
Equation 2.3 to calculate the overall yield loss:
Now, assume that the gain of the amplifier is specified to
. This requirement is typical for an amplifier
and by no means extreme in any sense. A gain of 0dB requires a resistor
ratio of 1:1. Inserting these values into Equation 2.4
gives:
Thus, the standard deviation of the resistor value is required less than 0.27% to fulfill the specification with good production yield. Such a matching in a standard CMOS process can only be achieved using optimal layout structures.
The nominal element ratio is defined by the geometries as drawn in layout. The actual ratio produced is a random variable with a mean in the vicinity of the desired value, and a standard deviation between 0.1% and 10%. The standard deviation is strongly dependent on the actual layout. The mismatch is influenced by a number of factors including: local process variations, global lithographic variations, local lithographic variations and process gradients[GT86][GC85][McC81][LHC86]. This holds for any kind of element (i.e. transistors, capacitors, and resistors). Therefore, similar techniques can be used to optimise the layout of any kind of element.