Figure 6.1: Poor power supply connection.
The first source of noise coupling or cross-talk is over the power
supply connections. Figure 6.1 shows a section of a mixed
analog-digital circuit, in which a common power supply is used.
At the point labeled `a', the voltage change is given by:
Figure 6.2: High speed data-bus driver.
To demonstrate how severe this problem is, consider the bus driver
shown in Figure 6.2. Assume an 8-bit wide data bus
with a rising edge requirement of 50ns loaded by 100pF. Further,
the power supply connection to the bus driver is 1mm long and
wide. At the initial switching of the buffer, a current
slew as high as 
can occur. This results in a
capacitor charging current of approximately 10-11mA[O'L91].
Inserting these values in Equation 6.1 gives a voltage
variation of 880mV. This reduction in the power supply voltages
reduces the noise margin of other digital circuits, perhaps to an
unacceptable level. For an analog precision block, such levels of
power supply noise is completely devastating.
Figure 6.3: Separate pins for analog and digital supplies.
The most obvious solution to the problem of noise coupling is to use
separate power supply lines for the digital and analog sections of the
circuit as illustrated in Figure 6.3. Unfortunately, this
solution requires extra pins, which may not be available. Care must be
taken, when using two separate power supplies, because of the danger of
bipolar latchup. If latchup is to be avoided, the VSS level must
be common external to the circuit for an N-well process
.
Figure 6.4: Separate bonding pads for analog and digital power supplies.
Figure 6.5: Separate routing for analog and digital power supplies.
Whenever separate pins are not available, the second best solution is
to use separate power supplies on-chip connected to different bonding
pads. The bonding pads are then bonded to the same pin as shown in
Figure 6.4. Some degree of coupling still remains, but
this type of connection does separate part of the common power supply
connection. The arrangement excludes the use of double bonding wires
for the supplies.
If double bonding wires to supplies are required, the only remaining possibility is to separate the power supplies on-chip and connecting together the supplies at the bonding pad. This situation is depicted in Figure 6.5. Using separate power supplies on the chip, connected to the same pad, cross-talk figures better than -90/-110dB at 10kHz have been achieved[O'L91].
Figure 6.6: Bonding wire inductance.
In addition to the supply strategies discussed above, the optimal selection
of pins on the package is crucial. For the power supplies, the
pins with the minimum inductance should be selected. The pin inductance
consists of two parts, the bonding wire inductance (usually <3nH) and
the lead frame inductance (see Figure 6.6).
The lead frame inductance is due to the connection from the bonding point
to the pin and is particularity large for dual-in-line packages with more
than forty pins.
A rule of thumb to estimate the inductance of a connection
is:
| Package type | Pin no. | Bond L [nH] | Bond C [pF] |
| 40 Pin Plastic | 1,2 | 15.0 | 2.4 |
| &10,11 | 4.4 | 0.7 | |
| 40 Pin Plastic | 1,2 | 18.6 | 2.6 |
| with socket | 10,11 | 7.6 | 0.8 |
| 40 Pin Ceramic | 1,2 | 20.9 | 2.7 |
| &10,11 | 9.0 | 0.8 |
Table 6.1 gives the measured inductance and capacitance for different pin placements of a forty pin dual-in-line package. The pins at the corner of the package have longer connections than the pins in the middle of the package and as a result, the pins at the corner have a higher inductance. The difference can be as large as a factor of three. This corresponds to 9.5dB lower noise spikes. The pads near the middle of the package should be used for power supplies and critical signals.
If a high speed data bus is required, the bus drivers should use a separate power supply pin. This pin should be placed between the data bus pins to minimise the power supply interconnection. In general, digital connections should be kept as far away from the analog circuit sections as possible.
Rather than trying to minimise the problem of high speed data buses, it is desirable to try to prevent the problem from occurring in the first place. This can be achieved using controlled edge buffers[Rav87]. Such buffers are designed to control the speed of the rising and falling edges of the output lines. The maximum slew rate at the output pad is limited not to exceed a tolerable limit. This limits the dynamic loading of the power supplies, thus reducing the disturbances on the chip.