Relative parameter variations in MOS current mirrors

  In Section 4.1, we analysed the simple MOS current mirror under the assumption, that the parameters V_T and were identical for both transistors of the current mirror. We concluded that the current amplification of the current mirror, B₀, did not depend on the values of the process parameters, only on the dimensions of the transistors. In this Section, the consequence of minor differences in these parameters is analysed in detail.

First assume, that the threshold voltages, V_T1 and V_T2, differ by a small amount, . The following notation is used:

Referring to Figure 4.1, the input voltage is calculated using Equation (3.2):

The output current is calculated using Equation (3.2):

B₀ denotes the desired current amplification. We realise that a difference in threshold voltage, , results in a relative error in the current amplification by

V_IN-V_T is the `designed' value . The relative error is minimised by

1. choosing a suitable, large for the effective gate voltage, V_IN-V_T,
2. using unit transistors, as the threshold voltage depends slightly on the transistor dimensions, especially for small transistors, and
3. using layout techniques (e.g. common centroid layout) in order to reduce differences in threshold voltages.

Now assume, that and C_OX are slightly different for the two transistors:

Using Equation (4.6), we calculate the resulting amplification of the current mirror:

Again, B₀ denotes the desired value, while B denotes the actual amplification. A relative difference in or C_OX results in a relative error on the current amplification:

Similarly, such relative errors may be reduced using compensating layout techniques, e.g. common centroid layout.

Similar considerations apply to systematic variations in the transistor dimensions, common to all transistors. We now assume that the drawn dimensions W and L of any transistor are altered by common, yet unknown, amounts. The effective transistor dimensions are:

Inserting this into Equation (4.6) expressing the current mirror amplification, results in:

Again, B₀ denotes the desired current amplification, achieved using the designed transistor dimensions. The relative error is

Errors due to systematic changes in transistor dimensions can be eliminated or reduced by

1. compensating for and during the design (values may not be dependable),
2. using large transistor dimensions,
3. selecting the smallest transistor dimension to be the same for both transistors in the current mirror, or
4. using unit transistors.

Unit transistors have been mentioned as a means of reducing errors due to threshold voltage differences and systematic transistor dimension corrections. The basic idea is to use identical transistors with channel length L_U and channel width W_U, i.e. all transistors are expected to have almost identical parameters. The influence of actual transistor dimensions on threshold voltage and current factor will be the same for all unit transistors.

If we imagine that transistor M₁ in Figure 4.1 is realised as Q unit transistors in parallel, and transistor M₂ is realised as P unit transistors in parallel, the amplification of the current mirror is

denotes the current factor of a unit transistor. In this manner, any rational current amplification can be realised precisely.