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02206 Design of Integrated Circuits
Laboratory Exercises |
An integral part of the lecture course is 8 one-hour laboratory
exercises. The lab exercises are a mandatory part of the course,
and approval of these exercises is required to enter the exam.
The exercises will be carried out in teams of two students, and
you will find the teams on the
DTU CampusNet.
Present at the exercises will be teaching assistant Georgios Plakaris,
who may assist you in specific problems you may encounter during your
exercise.
Each exercise includes
- Preparation, which must be completed in advance.
Please observe that students, who have not completed the
preparation adequately, can be expelled from the exercises.
- A one-hour laboratory work.
Students who fail to complete the exercise within the time assigned,
may use vacant terminals to complete the exercise later.
- A laboratory manual, reporting the exercise work.
The lab manual must be handed in to the teaching assistant the
first Friday after the exercises at noon.
The purpose of the laboratory exercises is provide the student with
the skills necessary to design and verify CMOS cells, subsystems,
and complete systems, from the layout level to the behavioral description
level.
The background material for the exercises consists mainly of
-
02206: Design of Integrated Circuits,
Practical Classes.
Informatics and Mathematical Modelling, DTU, 2002
-
Flemming Stassen, `Design Rules and Electrical Parameters
for a 0.18 micron CMOS Process'
Informatics and Mathematical Modelling, DTU, January 2002
-
02206: Design of Integrated Circuits, Course Project.
Informatics and Mathematical Modelling, DTU, 2002
The specific aims of each lab exercise, the required preparation as well as
the requirements for the laboratory manual, can be found in the first of
the references cited, `02206: Design of ICs, Practical Classes´.
The schedule of the laboratory exercises are
- Exercise 1, Tuesday 12. February 2002:
- Full custom layout basics
- Exercise 2, Tuesday 19. February 2002:
- Ripple carry adder cell (layout)
- Exercise 3, Tuesday 26. February 2002:
- Ripple carry adder cell (DRC)
- Exercise 4, Tuesday 5. March 2002:
- Ripple carry adder cell (simulation)
- Exercise 5, Tuesday 12. March 2002:
- Ripple carry adder cell (optimization)
- Exercise 6, Tuesday 19. March 2002:
- VHDL modelling (1)
- Exercise 7, Tuesday 2. April 2002:
- VHDL modelling (2)
- Exercise 8, Tuesday 9. April 2002:
- VHDL synthesis
[02206 homepage]
Modified by Flemming Stassen on 11 February 2002
stassen@imm.dtu.dk