Home page of Jens Sparsų

Jens Sparsų
Professor

Department of Applied Mathematics and Computer Science
Embedded Systems Engineering section
Technical University of Denmark
Building 322

DK 2800 Lyngby,
Denmark
e-mail: jspa AT dtu DOT dk

NEW: As of April 1, 2024 I have become Professor emeritus.
The department is hosting a farewell reception on May 16, 2024, 15:30 - 17:30. See invitation

This is my personal web-page.
I also have an official DTU web-page

Research Interests

Digital systems. Asynchronous circuits. Low-power design. Networks-on-Chip. Many-core architecture. Cyber physical systems.

Publications

An up-to-date publication is found on my official DTU web-page
I also have a profile in Google Scholar

I have co-authored what has become the standard textbook on asynchronous circuit design:

Jens Sparsų and Steve Furber (eds.),
Principles of asynchronous circuit design - A systems perspective.
Kluwer Academic Publishers, 2001.

In 2009 the book was translated into Chinese at the initiative of the Chinese Academy of Sciences.

As of 2006, Part I of the book, i.e.:
Jens Sparsų, Asynchronous circuit design - a tutorial, chapters 1-8,
is freely available for non-commercial educational use. [Go to download]

June 2020: NEW BOOK

Jens Sparsų,
Introduction to Asynchronous Circuit Design
DTU Compute, Technical University of Denmark
2020. (273 pages)

This is an updated and extended version of my tutorial on asynchronous circuit design.
The extensions include:
(i) improved coverage of data-flow components
(ii) a new chapter on two-phase bundled-data circuits
(iii) a new chapter on metastability, arbitration, and synchronization
(iv) a new chapter on performance analysis using timed Petri nets

With these extensions, the text provides more complete coverage of the field and it is now made available as a stand-alone book.
The book is available in two formats:

A free PDF-version (ISBN 978-87-643-2001-5) can be downloaded from the DTU Research Database.
It is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International (CC BY-NC-ND 4.0) License.
If you delete the cover-page(s) added by the DTU Library and print double-sided you have a book complete with front and back cover.
A paperback version (ISBN 979-86-550-5385-4) is published through Kindle Direct Publishing, and
sold by Amazon for a modest 11.00 USD.

Selected Publications

Z. Jelcicova , E. Kasapaki, O. Andersson, and J. Sparsų, "PeakEngine: A Deterministic On-the-Fly Pruning Neural Network Accelerator for Hearing Instruments," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol: ?, issue: ?, pages: ?, 2023 (Accepted).
J. Sparsų, H.J. Damsgaard, D. Katsamanis, D. and M. Schoeberl, "Comparing timed-division multiplexing and best-effort networks-on-chip," Journal of Systems Architecture. Vol. 133, p. 102766, 2022.
M. Schoeberl, L. Pezzarossa and J. Sparsų, "A Multicore Processor for Time-Critical Applications," IEEE Design & Test vol: 35, issue: 2, pages: 38-47, 2018.
E. Kasapaki, M. Schoeberl, R.B. Sųrensen, C. Müller, K. Goossens, and J. Sparsų, "Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol: 24, issue: 2, pages: 479-492, 2016.
I. Kotleas, D. Humphreys, R.B. Sųrensen, E. Kasapaki, F. Brandner, and J. Sparsų, "A Loosely Synchronizing Asynchronous Router for TDM-Scheduled NOCs," Proc. 8th IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 2014, pages: 151-158, 2014.
J. Sparsų, E. Kasapaki, and M. Schoeberl, "An area-efficient network interface for a TDM-based Network-on-Chip," Proc. of Design, Automation & Test in Europe Conference & Exhibition (DATE), pages: 1044-1047, 2013.
M.B. Stensgaard, and J. Sparsų, "ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology," Proc. ACM/IEEE International Symposium on Networks-on-Chip (NOCS), pages: 55-64, 2008.
S.F. Nielsen, J. Sparsų, and J. Madsen, "Behavioral Synthesis of Asynchronous Circuits Using Syntax Directed Translation as Backend," IEEE Transactions on Very Large Scale Integration Systems, (17)2: 248-261, 2009.
T. Bjerregaard, and J. Sparsų, "A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip," Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE), pages: 1226-1231, 2005.
T. Bjerregaard, and J. Sparsų, "A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip," Proc. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pages: 34-43, 2005.
Ö. Paker, J. Sparsų, M. Isager, N. Haandbęk, L.S. Nielsen, "A Low-Power Heterogeneous Multiprocessor Architecture for Audio Signal Processing," Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology, (37)1:95-110, 2004.
L.S. Nielsen, and J. Sparsų, "Designing Asynchronous Circuits for Low Power: An IFIR Filter Bank for a Digital Hearing Aid," Proceedings of the IEEE, (87)2:268-281, 1999.
L.S. Nielsen, and J. Sparsų, An 85 micro Watt Asynchronous Filter-Bank for a Digital Hearing Aid Proc. IEEE International Solid State circuits Conference (ISSCC), pages: 108-109, 1998.
L.S. Nielsen, C. Niessen, J. Sparsų, and C.H. van Berkel, "Low-power operation using self-timed circuits and adaptive scaling of the supply voltage," IEEE Transactions on Very Large Scale Integration Systems (2)4:391-397, 1994.
J. Sparsų, and J. Staunstrup, "Delay-insensitive Multi-ring Structures," Integration, the VLSI journal, (15)3: 313-340, 1993.
E. Paaske, S. Pedersen, and J. Sparsų, "An area-efficient path memory structure for VLSI Implementation of high speed Viterbi decoders," Integration, the VLSI journal, vol: 12, issue: 2, pages: 79-91, 1991.
J. Sparsų, H.N. Jųrgensen, E. Paaske, S. Pedersen, and T. Rübner-Petersen, "An area-efficient topology for VLSI implementation of Viterbi decoders and other shuffle-exchange type structures," IEEE Journal of Solid State Circuits, (26)2:90-97, 1991.

Journal style biography

Jens Sparsų (Member, IEEE) is a professor at the Technical University of Denmark (DTU). His research interests include: design of digital circuits and systems, design of asynchronous circuits, low-power design techniques, application-specific computing structures, computer organization, multi-core processors, and networks-on-chips - in short, hardware platforms for embedded and cyberphysical systems.
He has published more than 100 refereed journal and conference papers and is co-author of the book ``Principles of Asynchronous Circuit Design - A Systems Perspective'' (Kluwer, 2001), which has become the standard textbook on the topic. He received the Radio-Parts Award and the Reinholdt W. Jorck Award in 1992 and 2003 respectively, in recognition of his research on integrated circuits and systems. He received the best paper award at ASYNC 2005, and one of his papers was selected as one of the 30 most influential papers of 10 years of the DATE conference.
He has supervised 17 PhD students. Two are underway and 15 have successfully completed their studies. Among the latter, two are now in academic careers, and the rest have established successful careers in research and development in national and international companies.
He is a member of the steering committee the ACM/IEEE Intl. Symposium on Networks-on-Chip (NOCS).

Teaching

Currently (2019-20) I teach the following courses:

In the past I have developed and taught a range of different courses on:

Digital electronics ( 02138 Digital Electronics 1 and 02139 Digital Electronics 2 )
Computer architecture, based on the textbook by Hennessy and Patterson.
Design of VLSI systems; in the beginning based on the Mead & Conway approach and using the Berkeley tools (Magic etc.)

Students

Current:

Alessandro Cerioli (Ph.d. student, 2023-2026). Topic: Explore the realm of artificial and spiking neural network for audio applications. Principal supervisor. Co-supervisors: Prof. Martin Schoeberl and Prof. Luca Pezzarossa and from GN Audio: Dr. Tobias Piechowiak and Dr. Clement Laroche.
Riccardo Miccini (Ph.d. student, 2023-2026). Topic: Mapping high-level AI applications to artificial or spikingneural network architectures. Principal supervisor. Co-supervisors: Prof. Martin Schoeberl and Prof. Luca Pezzarossa and from GN Audio: Dr. Tobias Piechowiak and Dr. Clement Laroche.

Former:

Awards

Best Paper Award ASYNC 2005
Best Paper Award Finalist ASYNC 2009
Reinhold W Jorck Award 2003 (150 K DKK)
Radio Parts Award 1992 (60 K DKK)

Other Professional Activities

(List is not complete)

Member of the IEEE
Member of the steering committee for the ACM/IEEE Intl. Symposium on Networks-on-Chip (NOCS)
Technical Program Chair for ASYNC 2015
General chair and local organizer for ASYNC 2012
General chair and for local organizer for NOCS 2012
From 2005 to 2011 I was director of studies for the B.Eng. in IT study program, and I was a member of the Deans task-force that worked out a plan for the introduction of the CDIO-concept as the basis for all of DTU's B.Eng. study programs.
Technical Program Chair for ASYNC 2006.
During 1999-2003 I was the Director of the Thomas B. Thrige Center for Microinstruments. Download the final report in PDF-format
Program chair for PATMOS 1998
General chair for PATMOS 1997
Program chair and local organizer of ACiD-WG summer school on asynchronous circuit design 1997.

When I am not working ...

... you may find me on the water exercising, racing (one way or another), or simply relaxing and enjoying life.

Last updated March 2022