Thermal Management at Floorplanning Level

Relevant work in the area

• A. T. Winther, W. Liu, A. Nannarelli, and S. Vrudhula. "Thermal Aware Floorplanning Incorporating Temperature Dependent Wire Delay Estimation", Microprocessors and Microsystems (MICPRO), vol. 39, n. 8, pp. 807-815, Nov. 2015.

• W. Liu, A. Calimera, A. Macii, E. Macii, A. Nannarelli, and M. Poncino, "Layout-Driven Post-Placement Techniques for Temperature Reduction and Thermal Gradient Minimization", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 3, pp. 406-418, Mar. 2013.

• W. Liu, A. Calimera, A. Nannarelli, E. Macii, M. Poncino. "Post-placement Temperature Reduction Techniques", 2010 Design Automation and Test in Europe Conference (DATE 2010), p. 634-637. Dresden, Germany. March 2010.

• W. Liu, A. Calimera, A. Nannarelli, E. Macii, M. Poncino. "On-chip Thermal Modeling Based on SPICE Simulation", 19th International Workshop on Power And Timing Modeling, Optimization and Simulation PATMOS 2009, p. 66-75. Delft, Netherlands. Sept. 2009.

Modified by Alberto Nannarelli on Sunday November 06, 2016 at 18:07