Imprecise Arithmetic

Sometimes reducing the power dissipation of resource constrained electronic systems is a top priority. In signal processing, it is possible to have an acceptable quality even introducing some errors.

Degrading precision arithmetic Degradation is applied dynamically (at run-time) Disabling the lower (least-significant) portion of the datapath either by clock-gating or by forcing zeros. Lowering the supply voltage (VDD) and re-designing the carry-chains in the datapath to adapt to the increased delays. Disabling logic by power gating. Sloppy arithmetic Perform basic operations (e.g. addition and multiplication) in an imprecise manner by simplifying the hardware implementation to obtain a reduction in delay, area and power dissipation.

Original images JPEG decompressed (sloppy)

Work in the area

• P. Albicocco, G. C. Cardarilli, A. Nannarelli, M. Petricca, and M. Re, "Truncated Multipliers through Power-Gating for Degrading Precision Arithmetic", Proc. of 47th Asilomar Conference on Signals, Systems, and Computers, pp. 2172-2176, Nov. 2013.

• P. Albicocco, G. C. Cardarilli, A. Nannarelli, M. Petricca, and M. Re, "Imprecise Arithmetic for Low Power Image Processing", Proc. of 46th Asilomar Conference on Signals, Systems, and Computers, pp. 983-987, Nov. 2012.

• Electronic Appendix to "Imprecise Arithmetic for Low Power Image Processing" by P. Albicocco and A. Nannarelli. Nov. 2012.

• P. Albicocco, G.C. Cardarilli, A. Nannarelli, M. Petricca and M. Re, "Degrading Precision Arithmetics for Low-power FIR Implementation", Proc. of 54th IEEE Int'l Midwest Symposium on Circuit and Systems (MWSCAS 2011) , pp. 1-4, 2011.

• M. Petricca, G.C. Cardarilli, A. Nannarelli, M. Re, P. Albicocco. "Degrading Precision Arithmetic for Low Power Signal Processing", Proc. of 44th Asilomar Conference on Signals, Systems, and Computers, p. 1163-1167. Pacific Grove (CA), USA. Nov. 2010.

Modified by Alberto Nannarelli on Sunday November 06, 2016 at 18:10