Decimal Arithmetic

Computers resort to binary arithmetic to have a reduced number of components in order to save area on silicon and to reduce the space of the system. However, humans are used to deal with the decimal system and, sometimes, binary arithmetic is not so accurate in performing computation of decimals.

Binary floating-point cannot exactly represent decimal fractions. For example
10% = 10/100 = (0.1)₁₀ = (0.0001100110011001100110011001 .... )₂

For these reasons, financial applications implement decimal arithmetic operations in software and run much slower than the corresponding binary operations.

Nowadays, because of the shrinking of devices, it is realistic to design arithmetic units working in decimal arithmetic and to speed up operations done in the decimal system by several times. In the 2008 revision of IEEE standard 754, the specification to represent decimal floating-point numbers was added to the binary one.

Read more ...

• General Decimal Arithmetic (by Mike Cowlishaw)

• IEEE 754-2008 Standard (Wikipedia)

Work in the area

Decimal Floating-Point Unit

• A. Nannarelli, "Decimal Engine for Energy-Efficient Multicore Processors", Proc. of the 22nd Int.l Conference on Very Large Scale Integration (VLSI-SoC), Playa del Carmen, Mexico, Oct. 2014.

Decimal Division (DPD/BCD)¹

• T. Lang, A. Nannarelli. "A Radix-10 Digit-Recurrence Division Unit: Algorithm and Architecture", IEEE Transactions on Computers, vol. 56(6), pp. 727-739, June 2007.

• T. Lang and A. Nannarelli. "Combined Radix-10 and Radix-16 Division Unit", Proc. of 41st Asilomar Conference on Signals, Systems, and Computers, p. 967-971. Asilomar Hotel and Conference Grounds, Pacific Grove, CA, USA. November 4-7, 2007.
  ¹ DPD is Densely Packed Decimal and BCD is Binary Coded Decimal.

Decimal Division (BID)²

• T. Lang and A. Nannarelli. "Division Unit for Binary Integer Decimals", Proc. of 20th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP '09), p. 1-7, Boston, USA. 7-9 July 2009.

• S. Gonzalez-Navarro, A. Nannarelli, C. Tsen, M. J. Schulte. "A Combined Decimal and Binary Floating-point Divider", Proc. of 43rd Asilomar Conference on Signals, Systems, and Computers, Pacific Grove (CA), USA. Nov. 2009.

² BID is Binary Integer Decimal.

Decimal Multiplication (DPD/BCD)

• T. Lang and A. Nannarelli. "A Radix-10 Combinational Multiplier", Proc. of 40th Asilomar Conference on Signals, Systems, and Computers, p. 313-317. Asilomar Hotel and Conference Grounds, Pacific Grove, CA, USA. October 29 - November 1, 2006.

• L. Dadda and A. Nannarelli. "A Variant of a Radix-10 Combinational Multiplier", Proc. of 2008 IEEE International Symposium on Circuits and Systems (ISCAS), p. 3370-3373. Seattle, USA. May 18-21, 2008.