Tunable Floating-Point
Tunable Floating-Point (TFP)
is a floating-point format with adjustable significand and exponent fields bit-width
Features
- Significand m=[3, 24] bits (including hidden bit). Fraction f=m-1.
- Exponent e=[5,8] bits
- Rounding modes
- RTZ Round toward zero (truncation)
- RTN Round to the nearest (round up)
- RTNE Round to the nearest (tie to even)
IEEE 754 roundTiesToEven mode
- RTO Round to odd
- Customazible bias.
By custom bias can "skew" the dynamic range to increase precision.
TFP includes binary32 (m=24, e=8), binary16 (m=11, e=5),
Google's Brain-FP (m=8, e=8).
Motivation
- A flexible unit, handling a flexible format, can increase the power efficiency
- Operations can be approximated by reducing the precision
- Different precision/dyn. range in different parts of the algorithm
- Accuracy of reduced precision can be improved by rounding
Publications
-
A. Nannarelli.
"Variable Precision 16-bit Floating-Point Vector Unit for Embedded Processors",
Proc. of 27th IEEE Symposium on Computer Arithmetic (ARITH 2020),
p. 96-102. Portland, USA. 7-10 June 2020.
-
A. Nannarelli,
"Tunable Floating-Point Adder,"
IEEE Transactions on Computers, vol. 68, no. 10, pp. 1553-1560, Oct. 2019.
-
A. Nannarelli.
"Fused Multiply-Add for Variable Precision Floating-Point",
Proc. of the 32nd IEEE International System-on-Chip Conference (SOCC),
p. 342-347. Singapore. Sep. 2019.
-
M. Franceschi, A. Nannarelli and M. Valle,
"Tunable Floating-Point for Artificial Neural Networks",
Proc. of 25th IEEE International Conference on Electronics Circuits and Systems (ICECS 2018),
Bordeaux, France. Dec. 2018.
-
M. Franceschi, A. Nannarelli and M. Valle,
"Tunable Floating-Point for Embedded Machine Learning Algorithms Implementation",
Proc. of 15th International Conference on Synthesis, Modeling, Analysis
and Simulation Methods and Applications to Circuit Design (SMACD 2018),
p. 89-92.
Prague, Czech Republic. 2-5 July 2018.
-
A. Nannarelli.
"Tunable Floating-Point for Energy Efficient Accelerators",
Proc. of 25th IEEE Symposium on Computer Arithmetic (ARITH-25),
p. 33-40,
Amherst, USA. 25-27 June 2018.
-
A. Nannarelli.
"A Multi-Format Floating-Point Multiplier for Power-Efficient Operations",
Proc. of the 30th IEEE International System-on-Chip Conference (SOCC),
p. 351-356. Munich, Germany. Sep. 2017.
Modified by Alberto Nannarelli on
Wednesday October 04, 2023 at 11:49